Silicon engineering infrastructure
Coverage systems, methodology, simulator infrastructure, reset-safe architectures, scalable DV frameworks, and open-source silicon engineering tooling.
Thesis
Open silicon is entering its infrastructure phase.
For two decades, advanced silicon engineering infrastructure lived almost entirely inside proprietary EDA stacks. Coverage closure, debug visibility, methodology scaling, and sign-off flows were controlled by vertically integrated commercial tooling, and concentrated among a small number of very large organisations. That model is beginning to change: RISC-V, chiplet ecosystems, sovereign silicon initiatives, and AI-driven custom silicon have expanded the demand base for industrial-grade silicon development.
As that ecosystem grows, open infrastructure becomes strategically valuable, not just economically cheaper. The shared coordination layers RISC-V is creating turn silicon engineering infrastructure, debug tooling, and methodology into ecosystem assets rather than isolated proprietary capabilities.
The important question is no longer “Can open-source silicon tooling exist?” The important question is “Which layers of the stack become strategically open first, and which capabilities matter most for industrial adoption?” That is the lens through which I select technical work.
Silicon engineering is ultimately a risk-versus-cost decision: a team keeps verifying until the residual risk no longer justifies the cost of continuing. Coverage is the instrument that makes that call legible. On an open stack, that instrument is still being built.
Open infrastructure for teams that ship silicon.
Where I can help
The premium becomes a choice, not a tax.
Closed-source silicon engineering licences cost millions a year. Much of that buys capability the open flow now matches, and lock-in it can't. Where open wins is the part licences can't sell: code you can audit, extend, and own.
Advisory areas
- Silicon engineering strategy and organisation build-out
- Open-source verification adoption (pyUVM, CocoTB, Verilator)
- EDA vendor strategy and ROI realisation
- Engineering cost transformation and restructuring
- Engineering analytics and metrics functions
What I work on
Silicon engineering systems, open EDA, secure silicon, and infrastructure economics.
Open-source EDA
Contributions to Verilator and modern open silicon engineering flows around coverage instrumentation, FSM analysis, hierarchy-aware coverage, observability, and debug infrastructure.
Secure silicon systems
Pavona ecosystem work around secure silicon verification, access-control and OTP-controller verification, reset architecture, and Root-of-Trust DV infrastructure.
Silicon engineering economics
Commercial licences come with locks the invoice doesn't list: project-specific history trapped in a proprietary database, testbenches tied to one tool's dialect, per-seat fees renegotiated yearly from zero leverage. Open infrastructure turns the locks back into choices.
How the work fits together
Three layers, one job: generate the evidence, sharpen it, and turn it into a decision.
Most people own one of these layers; most executives own none of them directly. I work across all three: the testbench that generates the data, the tooling that improves it, and the analytics that turn it into a call on whether to ship.
Enabling layer — the environment
Evidence has to be generated before it can be trusted. The reset-safe UVM methodology in Pavona is that foundation: the testbench structure and stimulus that exercise a design thoroughly enough to measure how well it behaves. No foundation, no evidence. Shipped.
Produce — evidence you can trust
Every ship decision is only as good as the evidence behind it. My Verilator work raises that quality: catching what other tools miss, staying reproducible run to run, and resolving to each instance rather than a flattened total. Better evidence, better decisions. Shipped.
Consume — a residual-risk verdict
A pile of numbers is not a decision. UCIS as an interchange format, coverage merge and analytics, and open debug visualisation turn that evidence into the answer that matters: how much risk is left, and is it safe to stop? Roadmap.
What's in production
What's shipped, and where it lives.
The evidence: production infrastructure in Verilator and Pavona, merged and in use today. Strategy I set and code I wrote.
Verilator
Contributor of native FSM coverage to Verilator: state and arc coverage recovered directly from the RTL. Extended across non-enum, case-free, wide-encoding, and primitive-wrapper detection, plus determinism fixes, coverage-summary reporting, and per-instance hierarchy coverage.
Pavona
Contributor to the open secure-silicon distribution launched by GlobalPlatform. I authored a reset-safe DV library, access-control and OTP-controller verification, and the methodology documentation new engineers read: the UVM infrastructure guide, the reset-safe porting guide, RFC 2026-01, and the countermeasure verification framework.
A number your team can actually trust
My coverage work in verilator/verilator brought coverage reporting to the open flow where there was none, then made it complete, reproducible, and granular. Those are the qualities that let you rely on the number instead of second-guessing it.
The capability itself
Native FSM state and arc coverage, recovered directly from the RTL. A coverage type the open flow simply did not have.
Complete
Detecting the state machines other tools miss: non-enum state variables, case-free if/else chains, wide state encodings, and primitive wrappers.
Reproducible
Deterministic detection and stable tests, so the same RTL produces the same coverage number on every run.
Granular
Per-instance coverage rather than flattened totals. Counts preserved down to each hierarchy instance.
All credited to my name in Verilator's changelog. Verify with git log --author="ysekhar" on verilator/verilator.
Writing and research
Open silicon engineering economics, EDA market structure, and modular ecosystems.
I write and think about where open silicon is heading: the economics of open-source silicon engineering, the changing structure of the EDA industry, and the methodology that lets open flows reach commercial-grade rigour.
Open silicon & the EDA market
- Silicon Engineering: The Inevitability of Open Source
- Why pyUVM and Python-Driven Verification Will Disrupt the EDA Industry
- Precision at Scale: Data-Driven Semiconductor Engineering
- Embracing the AI Frontier — for Seasoned Silicon Engineering Leaders (I)
- Embracing the AI Frontier — for Seasoned Silicon Engineering Leaders (II)
- Embracing the AI Frontier — Harnessing Machine Learning & Deep Learning
- Embracing the AI Frontier — Essential Complementarities in Silicon
Methodology & secure silicon
Simulator & coverage infrastructure
The pull-request write-ups carry the full design rationale.
Background
Twenty years in silicon, EDA, and secure systems. MBA strategy lens.
I’ve spent more than twenty years in semiconductor engineering across silicon engineering, infrastructure, EDA, and secure silicon systems.
Experience includes zeroRISC, Imagination Technologies, Siemens EDA, Ericsson, Dialog Semiconductors, Arm, Broadcom, and Intel.
I also hold an MBA from the University of Chicago Booth School of Business, where my focus included strategy, platform economics, organisational scaling, and technology ecosystems.
That combination shapes how I think about open silicon infrastructure: not just as an engineering problem, but as an ecosystem and economic transition.
Selected leadership results
- $8M OpEx delivered through restructuring and vendor renegotiation
- $1.5M → $15M ARR account recovery; $65M cumulative five-year upsell
- Built and led engineering teams of up to 30 engineers across global multi-site organisations
- Technical Manager of the Year, three consecutive years
Strategic interest areas
Where I spend my attention.
Open-source silicon engineering infrastructure
Coverage systems and observability
pyUVM and Python-native DV
Secure silicon
Verilator internals
Silicon engineering methodology
RISC-V ecosystems
Infrastructure economics
Modular EDA systems
Scalable engineering systems
Software-native hardware engineering
Secure compute infrastructure